1. Field of the Invention
The present invention relates to a buffer storage control system in a processor, preferably a multiprocessor, and more particularly to a buffer storage control system including separately therein both a buffer storage for dealing with operand data and a buffer storage for dealing with instruction fetch data.
2. Description of the Related Art
A conventional processor, for example, a multiprocessor, includes a plurality of central processing units (CPU's), a main storage unit (MSU), and a main storage control unit (MCU). The MCU works to control data transfer between the MSU and CPU's.
Recent multiprocessors have featured very high-speed processing. This is achieved by introduction of a buffer storage unit, i.e., a so-called cache memory, into each CPU. The buffer storage unit momentarily holds therein some of the block data read from the MSU, so that the CPU can operate with the use of data held in its buffer storage unit.
In such a multiprocessor, it is important to maintain constant data coincidence between the MSU and the buffer storage units of all the CPU's. That is, if data in a buffer storage unit of one CPU is rewritten, the related data stored in the MSU and the buffer storage units of other CPU's, if any, must be invalidated or rewritten to include the same content. If such data coincidence is not maintained, data errors will clearly be produced by the multiprocessor.
In a multiprocessor of the type having both an operand buffer storage and an instruction fetch buffer, storage data coincidence must also be maintained to prevent such data error.
No simple technique to maintain data coincidence has been proposed, however.